Semiconductor processing technologies
Besides Atotech's R&D partnership at CNSE (USA) to develop new copper plating technologies for chip internal wiring, the advanced packaging approach is focusing on the electrolytic and electroless metal stack deposition for different wafer level packaging application.
Advanced Packaging
- Universal Pad Finish
- Through Mask Plating
- 3D Packaging
The Atotech advanced packaging approach benefits from Atotech's international organization and logistic structure with tremendous know-how from the electronic industry at all and with our subsidiaries in more than 30 countries. We can offer to the semiconductor industry our chemical processing know-how, electrolyte production experience as well as our globally acting support structure. The advanced packaging approach is focusing on electroless or electrolytically generated metal interconnections for different wafer level packaging application.
Miniaturization needs of interconnection technologies and corresponding higher I/O count as well as increased electrical demands on the signal path require innovative wafer level plating processes. Integrating electrodeposited copper
for wafer level packaging, such as redistribution layer (RDL) and copper pillar, provides several advantages, as there are:
- Fine pitch application,
- Effective signal transmission material
- Thermal stability
Furthermore for the cost effective production of semiconductor devices, the electroless generated bump process is providing the advantage of mask less metal stack deposition. The unique Atotech electroless universal pad finish can cope with both major application fields, as diffusion barrier for wire bonding application on aluminum and copper pads and as solderable surface finish for flip chip application. The major advantages are:
- Perfect corrosion resistance of metal stack
- High solder joint reliability
- Improved wire bonding reliability for high temperature application