Global Business Manager Surface Treatment Technology
Life as we know it is increasingly changing. More and more, electronic gadgets will fulfill various functions, autonomous driving, constant connectivity (IoT) supported by 5G networks, internet traffic and storage demands, as well as the way we manufacture things will not only increase exponentially but also change the world.
In order to support the continuous demand for improvement and optimization of electronics systems and components our industry calls for innovative and future-oriented solutions, which ensure high yield capabilities and increased packaging density (fine line capability) while reducing costs.
Atotech is at the forefront of developing future oriented solutions and has currently a number of products / projects which are designed to enable our clients to go above and beyond everything that is technically or commercially known, as of today.
Adhesion promotion – NovaBond® IT
NovaBond® IT is a revolutionary non-etching adhesion promoter for inner-layer bonding and soldermask pretreatment that combines the benefits of a non-etching treatment with enhanced peel strength and thermal reliability on standard ABF build-up films as well as liquid and dry film soldermasks.
Metallization – Printoganth® MV TP1 / PLP
Printoganth® MV TP1 / PLP are new electroless copper processes that provide highest throwing power into BMVs and their wedges enabling ultra-fine lines and spaces of >8/8 μm.
Electrolytic copper plating – InPro® SAP3 / Innolyte® PLP / Innolyte® P
InPro® SAP3, our new copper plating electrolyte development for advanced packaging (8/8µm L/S) and Innolyte® PLP for Fan-out Panel Level Packaging (5/5 µm L/S), both offer excellent line shape, filling performance and uniformity. For copper pillar plating in Fan-out Panel Level Packaging Innolyte® P provides highest plating speed with excellent uniformity.
Resist stripping – ResistStrip® IC
The ResistStrip® IC products are specially developed photoresist strippers that enable residue-free performance very fine line/space features (sub 15/15 µm) while minimizing copper or other metal attack.
Differential etching – EcoFlash® S200
EcoFlash® S200 is our latest differential etchant. This solution is based on iron sulfate and is specially designed to maintain the conductors undercut-free, enable yield improvement, lower line/space manufacturing and significantly reduce the use of chemicals.
Final finish – Pallabond®
PallaBond® is a pure EPAG future generation high-end finish with excellent solderability combined with high frequency, low signal loss attributes offering excellent wire bonding credentials.
Equipment – MultiPlate®
MultiPlate® is an innovative, fully automated electrochemical deposition plating system designed for flexible R&D and high-end application specific production. MultiPlate® can be customized for through hole filling, and both single and double side plating on RDLs and pillar structures, both of which are required processes for many new packaging applications.
As Global Business Manager for Surface Treatment Technology, I am especially convinced about our competencies and capabilities for bonding enhancement, advanced surface preparation, photoresist stripping and various adhesion promoters and etchants for fine line manufacturing. Atotech has always been at the forefront of adhesion technologies. Our BondFilm® process is the industry standard for inner-layer bonding. To remain market and technology leader we have introduced our newest and most advanced adhesion promoter to the market, NovaBond®IT. NovaBond®IT is Atotech’s solution for advanced substrate packaging adhesion requirements. By removing only 100 – 150 nm of copper to promote adhesion NovaBond®IT enables ultra-fine line and space capability below 5/5 µm, compared to current process of record which removes 0.8-1.0 µm of copper. NovaBond®IT also provides superior adhesion and thermal reliability with state-of-the-art build-up films as well as leading edge dielectric.
In this edition of our online newsletter, we especially highlight our new and cost-effective palladium reduction system for horizontal electroless copper applications, our study on identifying the best alloy compatible with the EPAG process suited for mobile applications and our systems solution for fan-out panel level packaging. We also look at our clean room production capability for advanced packaging, as well as give our view on the current developments in HDI PCB manufacturing.
Please contact us via: Web: atotech.beta.brettinghams-dev.de I Xing: www.xing.com/companies/atotech I LinkedIn: www.linkedin.com/company/atotech
With best regards
Global Business Manager Surface Treatment Technology
Publisher: Daniel Schmidt, Head of Electronics Marketing Worldwide
Editor: Yvonne Fütterer, Marketing Specialist Electronics
Neoganth® E Reducer
Cost-effective palladium reduction for horizontal electroless copper processes
Figure 1: Schematic drawing of the palladium-catalyzed self-decomposition of the reducer chemistry
Figure 2: Coverage performance of the new reducer system at different additive concentrations
As a global market leader, Atotech is striving for innovative solutions to sustain our customer’s business for the upcoming challenges of the electronics industry. In this respect, three overall objectives drive our product development: Sustainable solutions, technological leadership and cost-effectiveness.
Neoganth® E Reducer, Atotech’s new reducer process for our market leading ionic activation system Neoganth® fits perfectly to this philosophy. The palladium catalyzed decomposition of the active component in the reducer module, as illustrated in figure 1, is minimized.
This leads to three main benefits:
- Sustainability: The environmental impact of the reducer process step and, more precisely, the total amount of the active component (classified as toxic) in the waste water is minimized, thus reducing the amount of boron in the waste water.
- Process stability: Neoganth® E Reducer provides enhanced process stability and safety due to constant active component concentration in the reducer module.
- Cost-reduction: Chemistry consumption and thereby running costs are reduced significantly by approx. 25%. The actual required chemistry dosing per panel is determined by the intended chemical reaction (reduction of Pd2+ to Pd0) and the drag-out of the horizontal plating lines – and not by the self-decomposition of the active component.
The Neoganth® E Reducer process contains a special additive that deactivates the catalytically active palladium seeds accumulating in the reducer module over the bath lifetime. As a consequence, the consumption of the reducer chemistry is minimized due to a significantly decreased amount of active palladium particles for the decomposition reaction. Furthermore, the new process is compatible to all established pH buffer systems used by the industry.
During extensive TechCenter testing and customer qualification, the main focus besides the chemistry consumption was on coverage performance and the reliability of the overall electroless copper system. Figure 2 illustrates the coverage results evaluated by the backlight test for the reference system (Neoganth® WA Reducer) and different additive concentrations of the new Neoganth® E Reducer. The backlight performance – exemplary tested on five different base materials – was stable for all tested additive concentrations. In addition, the Neoganth® E Reducer system showed no failures in solder shock, quick via pull, thermal cycle or interconnect stress testing.
In summary, product qualification proofed the significant savings in reducer chemistry consumption at excellent reliability and coverage performance that are on a comparable level to the reference process Neoganth® WA Reducer.
Atotech’s Neoganth® E Reducer includes the following features:
- Two product reducer system: Neoganth® E Reducer (S) and Neoganth® E Additive
- It is applicable to horizontal electroless copper processes
- The Pd-catalyzed self-decomposition of the reducer is minimized
- It provides an excellent backlight performance, as proven in Atotech’s Uniplate® LB line
- Compatibility to all established pH buffer systems is given
- It fulfills the highest reliability standards (TCT, IST, SST, QVP)
- The reducer bath is fully analyzable
Summary and outlook
The new Neoganth® E Reducer process enlarges Atotech’s unique desmear and metallization product portfolio and contributes to the cost-effectiveness of our market leading process solutions for the entire PCB industry.
Sample plating capabilities are available in Uniplate® LB plating equipment located in Atotech’s TechCenter in South Korea.
For more information, please contact:
Assistant Product Manager Desmear & Metallization Atotech Deutschland GmbH
Phone: +49 (0)30 – 349 85 1573
EPAG process and LF 35 alloy for mobile applications
Data proves the superiority of this combination
Figure 1: Test matrix variables
Figure 2: A description of the physical test parameters
Figure 3: Summary of the IMC appearance and influence on SJR (250 µm, LF 35 Aged)
At Atotech, R&D is of high importance as our key focus is to be up-to-date and ahead of market developments and trends. In the market, an increase in I/O counts has led to ever decreasing cross sectional contact areas or, by default, an increase in solder performance expectations. High speed shear testing (HSS) is used to measure solder joint integrity. In response to the latest market developments, our surface finishing (SF) business technology team evaluated the solderability of the dominant final finishes in the market by using lead free solder balls to simulate production.
The following final finishes were looked at:
- Immersion tin (i-Sn)
- Organic Surface Protection (OSP)
- Electroless Nickel/ Immersion Gold (ENIG)
- Electroless Nickel /Electroless Palladium and Immersion Gold (ENEPIG)
- Electroless Palladium / Semi Autocatalytic Gold (EPAG)
Our team assessed whether the IMC is a good indicator of solder joint integrity and if the attributes form, size and composition of the IMC are important for predicting solder joint reliability (SJR). To analyze this, high resolution microscopy was coupled with High Speed Shear testing (HSS). HSS is used to artificially induce mechanical failure that is comparable to dropping the electronic device.
How did the SF team go about it ?
In order to represent the electronics industry, a cross section of final finishes, solder ball sizes (450µm and 250µm), alloys (SAC305 and LF 35), and thermal stresses (refer to figure 2), were employed. In addition to the traditional final finishes, a direct palladium on copper final finish was added to the mix (refer to figure 1).
A ‘cliff finding’ exercise was conducted to calibrate the tests. The details of the ‘cliff finding’ exercise are not important. However, significantly, the solder alloy behaved very distinctly during the test. The key take away message from this was that the solder joint generated with the LF 35 solder ball was significantly more ductile than that created by SAC 305.
What were the results of the high speed shear testing?
LF 35, which is relatively new to the market, proved to be well suited for mobile applications, due to its superior ductility. Many of the final finishes performed similarly before ageing independently of which solder alloy was used. The correlation between the fracture modes correlated closely with the total energy responses. The EPAG finish performed the best.
As an extra point of reference LF 35, 250 µm solder balls were included to amplify the responses from the 450 µm equivalents. This dimension highlighted that, apart from the OSP, the nickel free finishes performed the best when ageing was applied.
Comparing the HSS results to the IMC
The focus of this comparison test was on OSP, ENEPIG (thin Ni) and EPAG. In conjunction with 450 µm diameter SAC 305 solder balls and 450 µm and 250 µm diameter LF 35 solder balls, the following findings were made:
- The IMC formed by the OSP finish was fairly needle like and consistent.
- Results for the EPAG were similar to those of the OSP.
- For the ENEPIG (thin Ni) the IMC was even, but not needle like in shape and showed strong nickel corrosion with an associated phosphor rich band.
After ageing, the IMC for the OSP finish increased in thickness while the relative surface area decreased. The ENEPIG IMC also became thicker and the phosphor rich band became more pronounced with potential weaknesses becoming visible. The EPAG finish performed better than the other finishes but the IMC was not significantly different from the OSP IMC. The surface area for the EPAG IMC, however, could be considered larger.
During the ‘cliff finding’ exercise the ductility of the LF 35 was greater than the SAC 305. Therefore, in a next step, the correlation between the LF 35 alloy and the IMC formation was assessed. As with the SAC 305 the OSP and EPAG IMC appeared similar as received (ASR). The ENEPIG (thin Ni) IMC could be described as needle like but not continuous. The form seemed disturbed and the copper / nickel interface showed signs of strong corrosion.
In conclusion, the Total Energy (mJ) results were similar. The ENEPIG IMC (thin Ni), however, showed conspicuous copper corrosion. There was also an indication that there was more copper corrosion in the EPAG sample than in the OSP sample. This phenomenon appeared to have no detrimental impact on Total Energy (mJ).
What did we take out of this?
The result for the EPAG process was significantly superior to the other finishes discussed in this more stringent environment. The compatibility with the LF 35 solder places this finish well for mobile applications.
The study departed from the Total Energy (mJ) results as in this instant the fracture mode clearly demonstrated the suitability of the EPAG finish for mobile applications.
All data showed that the main influence on the soldering performance of the final finishes is the solder ball size. This can be attributed to a relative difference in the contact area. Another significant impact is the type of alloy used for the solder ball. All data indicated that the LF 35 alloy is better suited for mobile applications than SAC 350. It is also compatible with the EPAG process.
In terms of IMC comparison, the nickel free finishes are generally comparable. Those containing nickel are likely to create brittle IMCs. The exception in this test was the OSP, which performed poorly.
In essence, all the data reinforces the application benefits of the EPAG process over nickel containing final finishes. This is especially true when combined with the LF 35 alloy.
For more information, please contact:
Product Manager Surface Finishing at Atotech Deutschland GmbH
Phone: +49 (0)912 872-340
Innolyte® and MultiPlate® for FO panel level packaging
New cost reduction and package design possibilities
Figure 1: FO- Package-on-Package example for advanced processor application with tall Cu pillar, RDL and µ-via structures
Figure 2: WIPU results on a pattern 508 x 508 mm panel
Figure 3: Additives and current plating requirements
Fan-out wafer level packaging (FO-WLP) today is seen as a key advanced packaging platform which meets the technological and cost roadmap requirements of the industry. It is currently the fastest growing advanced packaging technology and will continue to grow towards a USD 2.4 billion market by 2020. Compared to main Package on Package (PoP) manufacturing solutions, the IO count of FO-WLP is not limited to the area of the die, thereby allowing finest package density. It also leads to better performance and a higher level of system integration. Figure 1 gives an example of required features in an integrated FO-PoP design.
The size of the manufacturing substrate is a key driver of the overall costs of a package. Substrate sizes beyond 300 mm would allow advantages in economies of scale in the packaging manufacturing processes, since more dies can be produced on a square panel than on a wafer. This offers new possibilities in package design and significant cost reduction potential (as standard panel manufacturing structures can be used).
This currently drives the industry and the supply chain – the transfer of FO-WLP to FO-PLP (Fan-Out panel level packaging) and the development of new products and solutions that make benefit of the substrate scaling possibility in order to reduce costs.
Equipment – MultiPlate® for panel level packaging
Atotech’s existing MultiPlate® equipment targets both approaches: wafer- and panel-level packaging. The electrochemical deposition plating system for panel level applications is designed for single and double sided plating, and high speed pillar plating. It is compatible with various panel size substrates (silicon, glass, etc.) and can be customized according to individual production requirements. Target applications include FO-PLP, advanced substrates, and interposer (2.5D and 3DIC) for Cu pillar and RDL processes.
Designed to meet current requirements, MultiPlate® features segmented, stable anodes and an advanced fluid delivery system. This allows the optimization of uniformity at high deposition rate and is ideal for small features and tall copper pillars. Furthermore, a specially developed version of Fe auxiliary redox system, a well-known feature of Atotech’s very successful Uniplate® IP2 platers, ensures pure deposits and a long, stable bath life. Latest plating results on glass and organic substrates with sizes of up to 510 x 515 mm achieved a WIPU well below ±10%.
Chemistry – The new Innolyte® product family
To meet the different technology requirements, Atotech has developed specific processes for Cu RDL and pillar plating consisting of high-purity organic additives. The new Innolyte® electrolytes are designed for very high-speed plating in Atotech’s MultiPlate®. This leads to the perfect combination of equipment and chemistry for FO-PLP, satisfying the technology needs by providing a high deposition rate together with achieving the requirements for Cu deposit.
Innolyte® P is a two additive electrolyte for tall pillar plating. The focus of the development was on high applicable current densities of about 20 ASD (A/dm²). By using pulse plating, a rectangular pillar shape can be achieved even at these high current densities. Of course very good within-unit and within-panel uniformity is a must.
For RDL plating, Innolyte® PLP has been developed. This process is focusing on within-unit distribution at current densities of >4 A/dm² for fine lines and pads while being able to fill µ-vias at lowest plated surface copper thickness. Figure 2 shows the results achieved on pattern customer boards sampled in our MultiPlate® Panel.
A summary of additives and current plating requirements for FO-PLP applications is shown in figure 3 (the with-in-panel distribution (WIPD) is calculated as follows: WIPU= ± max-min/2×mean × 100%).
Where do we stand?
Exploring panel-based manufacturing instead of the current wafer-based approach for Fan-Out packaging manufacturing offers potential for further cost reductions and increased productivity. Many augurs predict this is the way the industry is heading in its strive for better performance at lower cost as predicted by Moore’s Law. This task is not as easy as it seems. The yields and technology level from the silicon side must be merged with the existing infrastructure of the OSAT & substrate manufacturers.
The new developments in chemical processes and dedicated equipment for panel level applications showed their capability for next generation packaging. With the Innolyte® product family and MultiPlate® equipment, Atotech provides a clearly feasible and already available solution today.
For more information, please contact:
Global Product Manager Panel / Pattern Plating
Atotech Deutschland GmbH
Phone: +49 (0)30 349 85 -434
Semiconductor Advanced Packaging
Cleanroom production of chemistry and equipment for next generation technologies
Figure 1: Cleanroom production facility from viewing corridor in Neuruppin, Germany
Figure 2: Chemistry distribution system
Figure 3: Small parts ultrasonic rinse at cleanroom lock in Feucht, Germany
Figure 4: MultiPlate® – Sustainable production of next generation technologies
In an industry that is continuously evolving, Atotech strives to add value for customers by supplying high performance, top quality, and reliable production equipment and chemistries. Our focus on supplying technology-leading turnkey solutions and unparalleled customer service is made possible by our commitment to safe, sustainable, and efficient production, as well as our global approach to business, with TechCenters in over 11 countries equipped for local, on-site service and support.
Staying ahead of the competition and being able to address the industry’s requirements for next generation technologies has always been the foundation of Atotech’s global strategy. Our cleanroom production facilities enable us to manufacture chemistry and equipment that tackle these increasing demands. For the electroplating process in semiconductor packaging, the requirements for next generation technologies are:
- Pure metal deposits for improved voiding performance and reliability
- Optimized non-uniformity for high yield
- High speed plating of fine line features, enabling high throughput and increased miniaturization
From the point of raw material selection and qualification, to chemistry production in our state-of-the-art manufacturing facility, and finally to finished product quality testing, we control the quality of our chemistries at every production step. In doing so, we are able to manufacture high purity chemistries that comply with the most stringent requirements for semiconductor processing. With the addition of our cleanroom equipment manufacturing facility, we are now positioned to provide the semiconductor industry with a turnkey solution that delivers optimized plating results, and satisfies the aforementioned requirements for next generation products.
High purity chemistry production
Our 1,500 m² cleanroom facility for high purity chemistry production utilizes the latest engineering manufacturing technologies and employs closed loop production systems and advanced filtration for optimum particle control, production consistency and efficiency, and safety. This facility is ISO 6, ISO 9001 and ISO 14001 certified and is located in Neuruppin, Germany.
Semiconductor equipment production
Our industry-leading manufacturing facility for semiconductor equipment contains 2,250 m² of cleanroom production area and is located in Feucht, Germany. The ISO 7 cleanroom allows for fine line testing with high purity DI water, efficient particle control with constant air exchange and routine particle measuring and tracking. Humidity and temperature are controlled for optimized equipment production. Equipment manufactured in our cleanroom facility is specially designed to satisfy the high cleanliness standards and requirements for fine line capability, while enabling very high speed plating of next generation technology features.
As environmental regulations become more rigorous, we remain committed to our core values and the development of innovative and sustainable technologies that enable our customers to improve process efficiency and minimize their environmental footprint.
During production of semiconductor chemistry and equipment, all materials (plastic, PVC, stainless steel, etc.) are recycled, a heat recovery system is employed for 70% energy regeneration, and specialized cleaning and rinsing equipment are used that enable the recycling of the chemistries and precious metals, as as well as waste water reduction. Additionally, our chemistry is manufactured in close production systems in order to eliminate the risk of contamination to the external environment.
In addition to employing sustainable manufacturing methods, we strive to develop products that are sustainable and processes that are energy efficient. We continue to monitor environmental regulations and adjust our products accordingly. We also heavily invest in R&D for next generation technologies, with the goal to provide products that are free of CMR, toxic, and allergenic substances, as well as heavy metals. Our lead free nickel and cyanide free gold for pad metallization are two examples of products that exemplify Atotech’s commitment to the elimination of dangerous and toxic substances.
Another example is our MultiPlate® system, an electrochemical deposition tool that enables energy efficient electroplating with lower process temperatures, and both lower energy and additive consumption. Together with our high purity Spherolyte® chemistries, MultiPlate® enables a more efficient and cost effective method for embedding power chips by means of simultaneous electroplating on both sides of the wafer. Additional system features provide technical benefits for embedded technologies – such as better heat management and energy efficiency – and enable further miniaturization of power semiconductor packages to comply with future product requirements.
MultiPlate® is designed for single and double side plating, through via filling, and high speed pillar plating. The tool is compatible with both wafer and panel formats in a variety of sizes and substrates (silicon, glass, etc.), and can be customized according to the individual production requirements.
For more information, please contact:
Global Product Manager Semiconductor Advanced Packaging Atotech Deutschland GmbH
Phone: +49 (0)30 – 349 85 445
Manager Business Development Equipment worldwide at Atotech Deutschland GmbH
Phone: +49 (0)912 – 872 5633
The changing shape of the HDI market
New market needs challenge HDI PCB manufacturing
Figure 1: iPhone thickness and WLP development by generation
Figure 2: mSAP and amSAP process sequences
Figure 3: Impact of copper thickness on line and space capability
The long term growth forecasts for the printed circuit board market are in the order of 2% CAAGR until 2021 according to Prismark. This varies dramatically by region, so growth is fairly flat. High Density Interconnect (HDI), Microvia, IC Package Substrates and Flexible Printed Circuits (FPC) revenues all declined in 2016 as new designs are smaller and therefore less expensive.
The primary growth drivers for change are due to technology shifts towards smaller form factors and designs. This is not conducive to value or area growth.
HDI boards in mobile devices particularly in mobile phones are running out of space and must shrink to accommodate the need for increased space for batteries in our increasingly connected world. This has a number of effects on the HDI market in terms of requirements:
- Increased interconnection density by miniaturization of holes, pads and conductors is required to improve connection to the next system level
– IC substrate or direct chip attach
- This maximizes electrical performance, reducing latency, increasing signal speeds
– iEssential for mobile devices, Ultrabook’s and notebooks
- Smaller solder spheres and pads require a reduction in BGA pitch which, along with thinner PCB’s and die’s, raise concerns over warpage and solder joint reliability
In conjunction with all of these requirements improved shielding is needed with more components crammed into a smaller space. Shielding may also be incorporated into the HDI PCB going forward and improved thermal performance of the HDI PCB is driven by mobile devices to reduce heat dissipation.
This is quite a list of requirements for the HDI market. We have already seen the introduction of High Density Fan Out Wafer Level Packaging (FOWLP) in mobile devices with the advent of TSMC’s Integrated Fan Out (InFo) package combining an Applications Processor (AP) and Memory in a Package on Package (PoP) build on the Apple A10 processor in the iPhone 7. This eliminates the need for an IC substrate and has impressive performance metrics, higher system-level performance in a thinner package, at a cost.
Where is the market going?
Whether other mobile phone suppliers will follow suit remains to be seen, albeit it has been reported that Samsung will introduce similar technology in its next generation devices. We can assume for high end mobile devices that this will result in a huge increase in direct chip attach to HDI boards in the future.
Direct chip attach for InFo and others will result in a very low warpage requirement and an underfill requirement under the AP/Memory stack.
The tendency towards smaller, thinner PCB’s and die’s to improve mobile device form factor is clearly shown in the development of the iPhone thickness (Figure 1). The advances in HDI development and increasing levels of Wafer Level Packaging (WLP) in the devices enable this. The number of WLP’s has also significantly increased the reliability of mobile devices (Figure 1).
New laser drilling developments are required to ensure that smaller vias can be mass produced at reasonable cost and also to reduce the Heat Affection Zone (HAZ) in the dielectrics which limits via density.
New lasers with picosecond and femtosecond pulses are coming to market offering increased speed and productivity with improved quality and less HAZ at lower hole sizes. This is a critical development to enable ultra small microvias <25 µm in prepreg going forward. Improved surface treatments for copper to extend the life of CO2 Laser Direct Drilling (LDD) are also coming to the market.
Next generation designs for HDI will see a reduction to ≤30 µm line and space (L/S). This excludes semi panel plating techniques which have been the mainstay used in HDI production up until now. The PCB industry is already moving to modified Semi Additive Processing (mSAP) and advanced modified Semi Additive Processing (amSAP) to achieve this capability and to improve yields. Thinner copper foils are required and design rules also have to change to meet these requirements. Indicative process sequences for mSAP and amSAP are in Figure 2.
The reduction in copper foil thickness increases customer capability to produce fine L/S as the copper thickness on the dielectric is critical to both yield and L/S capability. Ultra low profile copper foils are also required which increase cost.
Challenges and solutions
Every aspect of HDI PCB manufacture is challenged to meet these market needs:
- Surface preparation and multilayer bonding
– LDD preparation, dry film adhesion and copper to dielectric bonding
– Small via desmear
- Electroless copper
– High throw electroless copper for small microvias
– Electrolytic copper
- Electrolytes capable of via filling and pattern plating simultaneously
– Through hole filling electrolytes
- Final finishes
– Must evolve to meet finer L/S requirements and smaller pad diameters to ensure solder joint reliability and electrical performance
For more information, please contact:
Marketing and Technical Sales Manager Electronics
Atotech Deutschland GmbH
Phone: +49 3034 985 1615
Trade show news
Global events and trade shows
Atotech participated in a number of key global events during the past few months. Here’s a quick highlight:
SE Asia Technical Conference 2017
The “South East Asia Technical Conference on Electronics Assembly”, an SMTA conference, is a globally renowned electronics assembly conference. It took place from March 28 to 30, 2017, in Penang, Malaysia. The show focused on the drive for smaller, more functional consumer electronics along with the need for highly reliable electronics applications.
At the show, Rick Nichols, Global Product Manager Selective Finishing at Atotech Deutschland GmbH, presented on ‘Soldering Immersion Tin’. A highly interested audience posed questions about the suitability of immersion tin for multiple soldering cycles and was interested to see how it fared, as a finish, compared to the immediately comparable finish: immersion silver. The benefit of the Horizon systems approach sparked special interest.
SEMICON China 2017
SEMICON China, which took place from March 14 to 17, 2017, in Shanghai, China, is one of the largest trade shows for the semiconductor industry. Every year the show attracts the major players of the global semiconductor industry.
Thus, Atotech was well represented and showcased its latest technology developments and solutions. Our product highlights were MultiPlate®, a versatile ECD plating tool for the next generation of advanced packaging, Xenolyte® Zincate CFA2, a universal pretreatment process, and Spherolyte® RDL/Pillar 3, a conformal copper pillar plating process enabling flat and recess free pillar plating.
Second from left: George Yang, Deputy VP Far East (China, Hong Kong, Taiwan) at the Opening Ceremony of the CPCA
CPCA Show 2017
The China International PCB and Assembly Show (CPCA) was held from March 7 to 9, 2017, at the Shanghai International Expo Center (SNIEC) in Shanghai, China. It is China’s International Circuit Electronics Exhibition, attracting around 50,000 visitors from all around the world each year.
As a leading global player in specialty chemicals, equipment and services, Atotech showcased some of its leading equipment lines in Hall 7.1 #7K06. Visitors could find out more about our ST-Line®, Uniplate® PLBCu6 for mSAP and Uniplate® PLB for amSAP. ST-Line® is specialized equipment for inner layer, outer layer and soldermask pretreatment. Uniplate® PLBCu6 is the solution of choice for mSAP technology, while Uniplate® PLB for amSAP is the industry standards desmear and electroless copper system for high-end applications.
IMAPS Device Packaging 2017
The IMAPS conference is a globally renowned packaging conference and took place from March 6 to 9, 2017, in Fountain Hills, USA. It is dedicated to Interposers, 3D IC & packaging, Fan-Out, wafer level packaging and Flip Chip, and engineered micro systems and devices. In this capacity exposure to the dominant OEMs and the chance to develop a deeper understanding of the existing and future high end markets is guaranteed.
Atotech’s Rick Nichols, Global Product Manager Selective Finishing at Atotech Deutschland GmbH, presented on ‘The Influence of Intermetallic Compounds (IMC) on High Speed Shear Testing with a Specific Interest in electroless Palladium / Autocatalytic Gold’. A committed audience witnessed the superior solder joint reliability performances of Atotech’s flag ship processes, Stannatech® and PallaBond®. This data driven presentation demonstrated the excellent performance of PallaBond® and therewith Atotech’s leading position in the field of selective finishing.
IPC APEX EXPO 2017
Atotech presented and showcased at the IPC APEX Expo 2017 in San Diego, USA, from February 11 to 16, 2017. This year’s show marked IPC’s 60th anniversary, with many activities and events surrounding the Expo. The show’s main theme was “Technology’s Turning Point” – where inspiration turns into innovation and education and technology into real-world success.
Of special interest to visitors at Atotech’s booth was the PallaBond® process, a nickel free final finish for fine lines and high frequency, as well as Stannatech® SF8, an immersion tin process for vertical processing. The presentation on “Soldering Immersion Tin”, held by Rick Nichols, Global Product Manager Selective Finishing at Atotech Deutschland GmbH, received much attention. In his presentation, Rick managed to dissolve a common preconception and proved that immersion tin actually does have a long shelf life and is a reliable solderable finish.
NEPCON Japan 2017
NEPCON Japan 2017 is one of Asia’s leading conferences in the field of Electronics Manufacturing. The conference consists of seven shows specialized in the essential areas of electronics manufacturing and R&D. Special focus this year was on the future of electronics, especially in the fields of automotive, wearable devices, robots and smart factories. More than 110,000 experts and professionals from a wide range of fields related to electronics manufacturing visited the three-day event. The show took place from January 18 to 20, 2017, at Tokyo Big Sight in Tokyo, Japan.
A clear highlight at the NEPCON Japan was automotive, as electric cars and ADAS are increasing the importance of electronics parts. Industry trends were also visible, such as the move to fan-out wafer level packaging (FO-WLP) for IC packages and PCBs. Market trends seem to indicate that the increase of FO-WLP and the decrease in IC substrate cannot be avoided. As a result, many processes and materials were introduced at the NEPCON Japan. At the same time, countermeasures from IC substrate manufacturing were widely discussed, such as fine lines down to sub 10/10 and core-less technologies.
Meet our experts and senior leaders at key global events coming up around the world:
C-Tex Show 2017
Date: May 17 – 19, 2017
Venue: Suzhou International Expo Center, China
Date: May 30 – June 02, 2017
Venue: Walt Disney World Swan and Dolphin Resort, USA
Date: June 07 – 09, 2017
Venue: Tokyo Big Sight, Japan
Market and Technology
At a glance report of all the important market and technology News you can’t miss
Glass substrate can be rolled-up for organic electronics
The bendable flexible material can be transferred directly from the melt to a roller for storage, and then be unrolled into a manufacturing line. Created by a consortium of Schott, Fraunhofer FEP, Tesa SE and Von Ardenne, at 150µm the glass is both bendable and stable, giving it advantages over plastics, metals or silicon in terms of optical quality, temperature stability, chemical consistency, gas porosity or mechanical resistance – and it can be made down to 25µm. This is a research project, with challenges to manage and overcome, said Fraunhofer. The team has already made significantly improvements in glass edge strength, and the partners are optimistic that they will be able to bring glass-on-a-roll to market.
Worldwide Flexible Printed Circuit Boards market is expected to increase at a CAGR of 11.0% by 2025
As per estimation in a new study by Transparency Market Research (TMR), the opportunity in the global flexible printed circuit boards market was USD 13.51 bn in 2016. This is expected to increase at a CAGR of 11.0% during the period from 2017 to 2025 and attain a value worth USD 33.39 bn by the end of the period of 2025. The demand for multi-layer flex circuits is expected to remain dominant during the forecasted period.
Global Chip On Flex market is expected to grow from USD 1437 million in 2016 to USD 1795 million by 2021
According to a study by Market Research Future (MRFR), the increasing need for small and flexible electronics and rapid technological progression for increasing the accuracy lead to be the major growth factors for the Chip On Flex market. The global Chip On Flex market is therefore expected to grow from USD 1437 million in 2016 to USD1795 million by 2021, at an estimated CAGR of 4.43%. Increased cost of raw materials in related industries along with the highly complex configuration acts as a major restrains for the market of Chip On Flex.
Global Printed Circuit Board Connectors Market – Analysis, technologies & forecasts to 2021 – OEMs shifting focus to development of autonomous vehicles
According to the “Global Printed Circuit Board Connectors Market 2017-2021” report by Research and Markets, the global printed circuit board connectors market is expected to grow at a CAGR of 3% during the period 2017-2021. This is mainly due to the latest trend and increasing demand for automotive electronics.
5 IoT trends to watch in 2017
The five key IoT trends to be watched in 2017 are LPWA (licensed spectrum low-power wireless access) technologies, which will hit the market this year. They open the door to low-cost, long-battery life devices for a variety of applications. Developer outreach programs will be of greater focus. Security will increase in importance. As instances of hacked IoT devices will increase, so will the importance of security as a prominent selling point. Integration of IoT data streams and machine-learning engines will move into focus. And IoT will drive service business models as early adopters explore ways of how to use IoT data and analytics to develop new, transformational business models.
Ibiden to power all of its Apple manufacturing with renewable energy
Apple manufacturing partner Ibiden is Apple’s first supplier in Japan to pledge the use of 100% renewable energy, spread across 20 new energy facilities. Ibiden will deliver over 12 megawatts of solar power, with a large portion coming from an array floating in a body of water in a converted lumberyard.
Three hot trends in printed and flexible electronics
According to IDTechEx, the three hottest sectors in printed electronics are: 1. Flexibility is a stronger driver than cost reduction. The trend to create value beyond cost reduction continues, especially towards flexible display development. 2. Goodbye PCBs, hello structural electronics. The transition from PCBs to structural electronics bears many opportunities for companies. 3. Hybrid electronics: Using the best technology for the application. Printed electronics includes a broad range of enabling technologies at different points of commercialization and maturity.
One step closer to transparent electronics
Transparent electronics is an emerging technology for printed circuit design. Recent advancements move us closer to realizing transparent electronics as a practical platform. Latest technical progresses also put us one step closer to practical transparent circuits, although there is still no perfect technology for generating transparent flex circuits.
Global solder flux market is expanding
The global market for solder flux is influenced by the sturdy rise in the manufacturing of PCB, fueled by the increasing production of computers and mobile phones across the world. Although the global market for solder flux may not grow smoothly in the near future, it is expected to grow from USD 213.2 million in 2015 to USD 367.3 million by 2024, swelling at a CAGR of 6.30% between 2016 and 2024.
India is becoming a hub for smartphone manufacturing in South Asia
India is becoming the fastest growing smartphone market in the world and its handset industry is poised to overtake America as the second largest market in the years to come. The mobile industry’s contribution to the country’s GDP is expected to grow from 6.5% to 8.2% by 2020. This growth potential of the mobile sector has resulted in the government taking measures to ensure manufacturing under its “Make in India” initiative, including policy changes.
Global PCB connectors market 2017-2021
Technovia’s analysts forecast the global printed circuit board connectors market to grow at a CAGR of 3% during the period 2017-2021. The report covers the present scenario and the growth prospects.
Global printed circuit board technologies market to reach USD 85.26 billion by 2015
According to a report offered by Research and Markets, the global PCB technologies market is poised to grow at a CAGR of around 3.5% over the decade, reaching USD 85.26 billion by 2025. The report analyses the global markets of PCB technologies across all the given segments on global as well as regional levels presented in the research scope and focuses on market trends, leading players, supply chain trends, technological innovations, key developments, and future strategies.
Global automotive electronic control unit market 2017-2021
In a report by Technavio’s analysts, the global automotive ECU market is forecasted to grow at a CAGR of 7.4% during the period 2017-2021. ECU is a computer that controls one or many electrical systems in a vehicle. Modern ECUs employ both microprocessors and microcontrollers depending on the computational requirements.
Global FPCB market to reach USD 27 billion by 2022
The global flexible printed circuit board market is expected to reach USD 27 billion by 2022, growing at a CAGR of 10.4% from 2016 to 2022. Demand for consumer electronic goods, Internet of Things (IoT), and FPCBs in automotive applications drive market growth, said Allied Market Research. Increase in demand for automated robots is expected to provide lucrative opportunities to market players. Multilayer FPCBs is expected to maintain an upwards trend throughout the forecast period. Rigid-flex FPCBs are also expected to witness significant growth, owing to the compact size and low power consumption.
How good PCB design works for IoT
The latest design and manufacturing techniques mean that not only does a PCB mechanically support multiple electronic components as substrates, but it also electronically connects them through conductive paths to achieve specific functions as designed, writes C. T. Kao of Cadence Design Systems. It is inevitable that the interaction among electrical, mechanical, and thermal behaviors, due to the integration of conductive and non-conductive materials in a PCB, will determine its performance and applicability. Looking forward, PCB design will remain as a key element in a variety of innovative electronic devices, components, and systems, for many years to come. How to obtain a clear picture and enough information of the convolution and interaction arising from various physical mechanisms will be crucial for the time to market and quality of the products.
Printed, organic & flexible electronics forecasts, players and opportunities 2017-2027
A report recently published by IDTechEx states that the total market for printed, flexible and organic electronics will grow from USD 29.28 billion in 2017 to USD 73.43 billion in 2027. The majority of this is OLEDs (organic but not printed) and conductive ink used for a wide range of applications; while stretchable electronics, logic and memory, and thin film sensors have huge growth potentials as they emerge from R&D.
Global smartphone shipments hit a record 1.5 billion units in 2016
According to latest research from Strategy Analytics, global smartphone shipments grew three percent annually to hit a record 1.5 billion units in 2016. Samsung maintained first position, followed by Apple and Huawei.