Daniel Schmidt
Head of Electronics Marketing Worldwide
Dear readers,
Welcome to the latest edition of our Semiconductor newsletter. In this issue, we provide you with key information on three of our highly discussed innovative products: MultiPlate® equipment, Xenolyte Zincate CFA2 and Spherolyte® Cu RDL/Pillar 3 processes.
MultiPlate® is Atotech’s revolutionary new manufacturing tool for next generation packaging technologies that offers the versatility and multi-functionality necessary to tackle the current and future challenges for optimal performance in advanced packaging technologies.
Another major milestone for us this year has been the process development of a new acidic process for universal aluminum pretreatment (Xenolyte Zincate CFA2), to treat all aluminum type surface with just one process. It is deployed in the pre-treatment step before electroless nickel is applied as part of an ENIG or ENEPIG process.
Our new Spherolyte® Cu RDL/Pillar 3 process suits the current and future demand for next generations of Flip Chip packages with sub 45 nm node technology. The new generation of Flip Chips cannot be connected to substrates anymore by solder bumping technology, simply due to pitch limitations. They require Cu pillars with a solder tap as interconnection technology. To meet this demand, Atotech introduced a new generation of Copper Pillar process as the Copper built up is an essential part of the process and often one of the main bottlenecks in terms of productivity.
Ever since the launch of our three new innovative products recently, we are encouraged by the overwhelming interest our customers have shown in them. It further inspires us to innovate, rethink and challenge the conventional norms and further push the boundaries.
Lastly, please join me in welcoming Harald Ahnert, who has been appointed the Vice President of Atotech’s Electronics division. Harald is no stranger to Atotech. He has led a number of key leadership positions across the board and will now be spearheading our Electronics and Semiconductor strategy. Uwe Hauf, who led the Electronics and Semiconductor division successfully for over 10 years, will take on new responsibilities as the Chief Technology Officer.
We sincerely hope that you find this newsletter informative, interesting and useful.
Very best regards,
Daniel Schmidt
Head of Electronics Marketing Worldwide
Figure 1: Embedded Power Chip
Figure 2: (Right, left) Double side plated embedded power die; source: Fraunhofer IZM in collaboration with EmPower program
Figure 3: Example of FLWPL
Figure 4: Example of flip chip with copper pillar
Figure 5: (Left) Example of 20 μm Cu pillar plated at 3.8 μm per minute; (Right) FIB cut through the pillar
Figure 6: Atotech MultiPlate®
Figure 7: Tool process capabilities of the manual system offered by Atotech’s MultiPlate®. THF: Through Hole Filling
Product highlights
MultiPlate®
An ECD tool for next generation packaging technologies
As device geometries continue to shrink, semiconductor packaging technologies face continuous challenges to remain relevant and economically viable. Pressure on the entire supply chain is mounting and the drivers are clear – enhanced performance, more functionality, and reduced costs. The limitations of Moore’s law are well known and advanced technology nodes are no longer providing a significant cost reduction. Investments in next generation node technologies are perhaps too substantial and precarious and thus, the industry is turning to advanced packaging to enable improved performance and functionality, following the “More than Moore” approach.
While it is still unclear which of the advanced packaging technologies offer the best performance at the lowest cost, it is critical that companies actively engage and examine the variety of options, as opportunity costs are significant. Accordingly, there are a great number of R&D assessments being undertaken, using a variety of packaging applications, for example fan out wafer level packaging, flip chip, wafer level chip sized package, embedding dies, among many others. One key challenge for packaging researchers and manufacturers is to develop technologies that are innovative, aligned with market trends and future requirements, and of course profitable, all while minimizing opportunity costs. Thus, there is an urgent need to develop innovative technologies to satisfy the future challenges for advanced packaging and that also cost effectively address the emerging requirements. This excerpt will discuss some of the key challenges in advanced packaging and how they can be overcome with a novel approach to electroplating.
Embedding components in power chips
For assembly technologies in power chips, embedding dies has been identified as a promising solution for enhancing performance and reducing manufacturing costs. Embedding dies refers to the integration of components (passive components and integrated circuits) within the layers of a die package, see figure 1. Market research on embedded active and passive dies demonstrates that this technology will witness wide acceptance in the coming years, particularly for mobile and automotive applications.
Substrates with embedded dies offer smallest form factor and footprint, as the die package is significantly denser and therefore takes up less space on the PCB or IC substrate. Moreover, the process sequence, and in particular the number of plating steps, is shortened when dies are embedded and electroplated on both sides. There are a number of other benefits of embedding dies, including higher levels of integration and improved thermal and electrical performance. Embedding dies facilitates a shorter electrical path, which results in a faster signal and overall electrical performance for the entire package. Embedding dies also presents the opportunity for increased levels of integration and the ability to house multiple dies, of various functionalities, in a single package. Typically, during the embedding process, RDLs and backside metallization are done by sputtering and plating each side of the wafer or panel individually. This is a costly and equipment intensive exercise that can also slow down the production flow.
Advanced Cu deposition will continue to be a mainstay in advanced packaging, but not without some limitations. A primary concern regarding Cu deposition is the fact that as the substrate thickness decreases and thicker Cu RDL layers are required (in FOWLP, for example), warpage is a critical processing challenge. Double side plating – which refers to the simultaneous plating on both wafer/ panel sides, as shown in figure 2 – is able to overcome the warpage which is typical in high end processing with stress compensation achieved by simultaneous Cu depositions. The advantage here is significant, as warpage has a major impact on yield. Yield is also a challenge for panel-based manufacturing of embedded components. Notwithstanding, high volume manufacturers have already adopted embedded technologies for low I/O dies on panel-level. Yield will be discussed further in the next section.
Fan out wafer/panel level packaging
One example of embedding dies is fan out wafer/panel level packaging, figure 3. Fan out is a preferred packaging approach as it is designed to considerably increase I/O density with a reduced footprint and profile, partly due to the fact that it’s thinner than flip chip, as it does not require a package substrate.
Warpage is a critical processing challenge in fan out due to the use of thinner substrates and thicker Cu depositions. Yet another challenge is posed due to the lack of infrastructure. Both the equipment and complete fabs are unable to handle thin wafers and panel format, while continuing to provide desired yield. Fan out processing may soon be done on panel level, as the price per piece significantly decreases from larger wafer sizes to panel. However, standard panel tools are not designed for processing wafers and tend to have a significantly lower yield than their wafer counterparts. This is partly due to the design of panel tools and the fact that they have not been engineered to satisfy the highest ISO standards.
Atotech’s new ECD tool MultiPlate® has a double side plating capability that enables simultaneous plating of vastly different structures on each wafer or panel side, such as large pads for the back side metallization and fine lines of the RDL structures. MultiPlate® is designed to satisfy the stringent requirements for next generation advanced packaging applications, both on wafer and panel level, and can also be customized according to the customers’ production requirements. With its double side plating capability, it also effectively addresses the warpage issues which are common with embedded components.
High speed copper pillar plating for flip chip
Traditional wire bonding is being surpassed by flip chip as the preferred packaging application for sub 45nm node technologies. Flip chip is technically superior to traditional wire bonding which requires a larger footprint and offers limited I/O density. More importantly, thermal and electrical performances are significantly improved with flip chip. For the most advanced technology nodes, the preferred interconnection technology in flip chip is Cu pillar.
The standard process requirements for pillar plating include exceptional void performance, nonuniformity of less than 5 percent, and high current density plating at 10+ ampere per square decimeter (ASD). Each of these parameters contributes to the overall throughput, reliability performance, and yield for the plating process. Therefore, it is essential to develop a pillar plating technology that can deposit pure Cu with high deposition speed, without impacting the voiding performance and uniformity, both of which influence the electrical performance.
Atotech’s unique MultiPlate® in combination with their high purity chemistries satisfies all of the performance requirements for Cu pillar applications and provides a higher throughput than standard process of record, with a system throughput capacity of 50 wafers per hour. Using reverse pulse plating, the process is optimized to the desired pillar profile and shape, thereby reducing doming or dishing, and improving the overall uniformity of the deposited Cu (< 5 percent WIP/WID/WIW).
In MultiPlate®, deposition is significantly faster (≥20 ASD) than traditional fountain platers (≤10 ASD) and voiding performance is enhanced. Pure Cu depositions are made by possible by use of high purity chemistries and close monitoring of the bath components during plating. All of this is achievable because of the technically superior design of the system.
About MultiPlate®
MultiPlate® is a next generation plating tool that offers the versatility and multi-functionality necessary to tackle the current and future challenges for optimal performance in advanced packaging technologies.
Built for flexible R&D and high end application-specific production, MultiPlate® can be customized for through via filling, and both single and double side plating on RDLs and pillar structures, both of which are required processes for many packaging applications, see figure 7.
*DSP: Double Side Plating, RDL: Redistribution Layer, and Pillar
*Double side plating refers to the simultaneous plating of both substrate sides
For high end ECD processes, yield, throughput and reliability performance are enhanced when the chemistry, process, on-line analytics, and equipment are in synchronization. With the addition of MultiPlate®Atotech now holds the unique position of offering customers a one-stop-shop for electroplating, providing high purity chemistry, plating equipment, and process development for ECD packaging applications.
This paper was featured in Silicon Semiconductor’s March 2016 issue. To read the full paper, please click here.
For more information, please contact:
Cassandra Melvin
Global Product Manager
Semiconductor Advanced Packaging
Atotech Deutschland GmbH
+49 (0)30 – 349 85 445
cassandra.melvin@atotech.com
Figure 1: Xenolyte Zincate CFA2 process
Figure 2: Treatment sample with Xenolyte Zincate CFA2
Product highlights
Xenolyte Zincate CFA2 process
Atotech’s new acidic process for universal aluminum pretreatment
Currently, there is a large variety of Al-alloys used in the industry as interconnect material – spanning from pure Al, AlCu, AlSi to AlSiCu alloys and more. These materials need to be connected during the packaging process to other metals as Nickel, Cu etc. Before that can be done aluminum type surfaces have to be transformed into a zinc surface. And this specific treatment is called Xenolyte Zincate CFA2 process, which removes oxide layers, prevents reoxidation and ensures a reliable adhesion to the adjacent materials.
Atotech recently developed a new acidic universal Xenolyte Zincate CFA2 process to treat all aluminum type surfaces with just one process. It is deployed in the pre-treatment step before electroless nickel is applied as part of an ENIG or ENEPIG process.
Benefits of the new acidic universal aluminum process:
- One for Al(l): all types of Al can be treated with a single process flow
- Compatible with polyimide passivations
- No silver migration – no silver additives
- No amines – no cross contaminations by volatile products
- Room temperature process
Process description: Universal acidic Xenolyte Zincate CFA2
The process (figure 1) involves two treatments before the zincation treatment can be performed. Xenolyte Zincate CFA2 is performed twice. The first Zincate layer is applied and removed right away. Thereafter, the same process is repeated and zincate is re-applied. Double zincation ensures a smooth and regular deposit. A thin zinc layer of approximately 30-40 nm is built up.
After the second zincation, a layer of electroless nickel is applied. The nickel is completely replacing the zincate layer by an immersion process and can be built up to 3-5 µm.
Treatment examples
The first example (as shown in figure 2) is a treatment of a pure Al wafer treated with conventional zincation compared to Atotech’s new universal acidic zincation followed by e’less nickel deposition. The standard zincation results in non-closed nickel layer reflecting an irregular zincation process whereas the new Xenolyte Zincate CFA2 process delivers a regular and closed nickel deposit.
The second example is a 1:1 comparison for an AlSi (0, 5 %) Si) wafer with PI passivation (cross hatched structure) after treatment in alkaline and the new acidic Xenolyte Zincate CFA2 process, followed by electroless Ni plating. These wafers are especially difficult to handle as AlSi itself is one of the most demanding surfaces and Polyimide is sensitive to alkaline pH: Our new acidic process supplies a regular and dot free surface whereas the alkaline treatment known also as being very powerful fails to deliver proper results.
Summary
The new acidic universal Xenolyte Zincate CFA2 process delivers a reliable pretreatment for all Al type wafers for subsequent metallization. It is compatible with PI passivations and resists and does not contain any migration metals (Ag).
For more information, please contact:
Bernd Roelfs
Global Product Manager
Semiconductor Advanced Packaging
Atotech Deutschland GmbH
+49 (0)30 – 349 85 965
bernd.roelfs@atotech.com
Figure 1: Section of a typical Cu/SnAg pillar. Pillar is built up by Cu and the solder tap (SnAg)
Spherolyte® Cu RDL/Pillar 3 – Key benefits: Pillar profile and purity
Figure 2: Key benefits of Spherolyte® RDL/Pillar 3
Product highlights
Spherolyte®Cu RDL / Pillar 3
Next generation copper pillar plating
Smaller and faster, that’s the name of the game for the next generations of Flip Chips. But to achieve ‘smaller and faster’ often requires a dramatic shift in the technology – which is exactly the case with Flip Chip packages with sub 45 nm node technology. The new generation of Flip Chips cannot be connected to substrates anymore by solder bumping technology, simply due to pitch limitations. They require Cu pillars with a solder tap as interconnection technology (see figure 1). Strictly speaking, Cu pillars is not a very new technology, but the demand for this technology is rising sharply. Several new players with advanced technology variations are coming up with a huge demand for faster and simplified processes with the benefit of increased capacity. To meet this demand, Atotech introduced a new generation of Copper Pillar process as the Cu built up is an essential part of the process and often one of the main bottlenecks in terms of productivity.
Spherolyte® Cu RDL/Pillar 3 – Key benefits: Pillar profile and purity
The benefits of our new system are best understood by comparing our two processes for Cu pillar plating:
Spherolyte® RDL/Pillar 2 vs. Spherolyte® RDL/Pillar 3:
Spherolyte® RDL/Pillar 3 is now qualified at major OSATs in Asia for new high speed Cu Pillar application whereas Spherolyte® RDL/Pillar 2 is the POR for many customers plating RDL and Pillars with the same chemistry and as such in volume production for more than a million wafers/year. Both systems can be plated with high current densities of 4 µm/min or more with exceptional uniformity values of less than 5% within wafer or within die as it is generally expected for this technology.
Pillar Profile:
Its main benefit is the perfectly flat profile for RDL and pillars at high deposition speed. This flat and conformal plating shape ensures best profiles but does not allow to plate pillars which are embedded in the dielectric materials as depicted in figure 2. Here our new process Spherolyte® RDL/Pillar 3 is the solution: The improved performance is largely due to a completely new leveler system.
Purity:
The most distinctive improvement for our new RDL/Pillar 3 system is its inherent purity of the deposit (see figure 2). The Cu deposit has a magnitude lower level of incorporated impurities which are usually coming from the organic additive system. TOF–SIMS measurements of plated Cu deposits reveal a 10-20 times lower total impurity level. The main benefits of such a pure Cu deposit are:
- Lower void rate after thermal exposure as multiple reflow or temperature cycles
- No need for a nickel diffusion barrier between Cu and solder anymore.
- Lower stress rate
A comprehensive comparison between our systems with more details especially for the void topic can be found in the March issue of Chip Scale Review (Pages 20-24). To read the full paper, please click here.
For more information, please contact:
Bernd Roelfs
Global Product Manager
Semiconductor Advanced Packaging
Atotech Deutschland GmbH
+49 (0)30 – 349 85 965
bernd.roelfs@atotech.com
Corporate news
New leadership
Join us in welcoming Harald Ahnert as the new VP Electronics and Uwe Hauf as Atotech’s CTO
Harald Ahnert | VP Electronics, Atotech
We are delighted to share that effective 1st of April, Harald Ahnert has been appointed the Vice President of Atotech’s Electronics division and will be spearheading our electronics business globally. With close to two decades with the company, Harald is no stranger to Atotech. He joined Atotech in 1997 and since then led a number of successful projects, built strong customer partnerships and held key leadership positions across the board in Electronics and General Metal Finishing. In his previous position as Managing Director Harald led Atotech’s activities in Germany, the Netherlands and Austria.
Atotech’s President Reinhard Schneider said:
“In a dynamic and often volatile business environment, succession planning for our electronics division was particularly crucial for us. It was important for our company to appoint someone who has a broad understanding of the global market requirements and future trends along with a strong commitment to our customers’ expectations and goals. Since the initial years, Harald has been deeply involved in our Asian business. His experience within the Asian environment and strong customer focus are certainly important to Atotech.”
Uwe Hauf | CTO, Atotech
As we welcome Harald, we would like to express our gratitude to Uwe Hauf for his outstanding leadership and vision in successfully steering our Electronics business over the past 10 years. Uwe, who has been with Atotech for over 25 years, will continue to play an important role in the company – this time as the Chief Technology Officer.
In his new role, Uwe will be responsible for ensuring the efficiency of Atotech’s development procedures and practices in order to catalyze a fast time-to-market approach.
“Uwe has been indispensable to Atotech’s success. He continually brings an exceptional leadership style along with wealth of knowledge, which has impacted both us and our customers. As someone who thrives on new challenges, we could not have found anyone better than Uwe to lead our new initiatives,” added Mr. Schneider.
Both, Harald and Uwe will be based at Atotech’s head-office in Berlin.
For more information, please contact:
Daniel Schmidt
Head of Global Marketing Electronics
Atotech Deutschland GmbH
+49 (0)30 – 349 85 423
daniel.schmidt@atotech.com
Trade show news
Global events and trade shows
Past event
Atotech participated in a number of key global events during the past few months. Here’s a quick highlight:
SEMICON CHINA 2016
Atotech participated at this year’s SEMICON China, held in Shanghai from March 15 -17. SEMICON China is a premium event that attracts buyers from IDM, foundry, fabless, and OEM across the world. This year there were 6 key themes covered at the event and close to 868 exhibitors participated. Besides showcasing the offerings, the event is also an opportunity to get an insight into China’s semiconductor industry – which is currently going through an unprecedented growth prospects by the arrival of new industrial policies, global collaboration and supply-chain integration.
At this year’s show, visitors were particularly interested to know more about Atotech’s new offering MultiPlate® – a unique solution for next generation packaging technologies. MultiPlate® has a double side plating capability that enables simultaneous plating of vastly different structures on each wafer or panel side, such as large pads for the back side metallization and fine lines of the RDL structures.
SEMICON TAIWAN 2016
Atotech recently exhibited in SEMICON Taiwan 2016 – the premier event in Taiwan for microelectronics manufacturing. The event is well-respected in the region for connecting companies, people, products and information shaping the future of design and manufacturing for semiconductors, nanoelectronics, MEMS, photovoltaics and related advanced electronics.
A number of Atotech’s leaders and experts were at the show talking about our new offerings and innovative ways to tackle the challenges facing the semiconductor industry. The show is a rare chance to learn more about our newly launched MultiPlate® – An ECD tool for next generation packaging technologies. In addition, customers showed great interest in our new Spherolyte® Cu RDL/Pillar 3 process as well as Xenolyte Zincate CFA2, which is a new acidic process for universal Aluminum pre-treatment to treat all aluminum type surface with a single process.
SEMICON EUROPA 2016
To gain FREE admission to the show
use this code: SCEU-g4Nyx
Upcoming events
Meet our experts and senior leaders at key global events coming up around the world:
IEMT – EMAP 2016
Date: 20 -22 September, 2016
Venue: G-Hotel, Penang, Malaysia
2016 IWLPC
Date: October 18 – 20, 2016
Venue: San Jose, California, USA
SEMICON EUROPA 2016
Date: October 25 -27, 2016
Venue: Alpexpo, Grenoble, France
Booth #966
SEMICON JAPAN 2016
Date: December 14 -16, 2016
Venue: Tokyo Big Sight, Japan
Industry News
Market and technology
At a glance report of all the important market and technology News you can’t miss.
Atotech expands its Asian operations
With an initial investment of RYM 50 million (EUR 11 million), the new facility will cater to the growing demand of Atotech’s solutions in South East Asia.
Atotech has inaugurated its new plant in Penang, Malaysia. The announcement comes just months after the company invested heavily in a new equipment production facility in Guangzhou, China – underlining the growing demand for its products and solutions in the region. The new facility encompasses a built-up area of 7’500 sqm and a full production capacity of 12’000 t/a at single-shift operation. The operations will create an additional 35 new jobs, which are expected to increase further within the coming years.
Source: http://evertiq.com/design/38908
Global semiconductor market is forecasted to fall slightly to $327 billion in 2016, rebound in 2017 and 2018
Worldwide Semiconductor Trade Statistic (WSTS) expects a 2.4% fall of the global semiconductor market to $327 billion in 2016, with growing return in 2017 and 2018. Despite a slight increase in optoelectronics, sensors and analog the drop is mainly driven by declines in Memory and Logic, with the largest regional drop down in Americas.
Source: http://www.wsts.org/PRESS/Recent-News-Release
IoT drives worldwide 200mm fab capacity in 2018 reach back to former levels
While Logic/MPU and Memory device production migrated to 300 mm fabs, the 200mm capacity will grow again and reach 5.43 million wafers per month in 2018. This change is driven by IoT technologies, such as display driver IC, CMOS image sensors and MEMS manufactured in Foundries.
Source: Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI
http://electroiq.com/blog/2016/02/foundries-takeover-200mm-fab-capacity-by-2018/
New chip-packing technology to take on TSMC in chip-packaging technology
Samsung Electro-Mechanics has developed a new chip-packaging technology, a type of Fan-Out wafer level package (FoWLP) to intensify competition with TSMC to gain more orders for application processors used in iphone 7S. TSMC was earlier named as sole supplier using 10nm manufacturing technology with up to 60% yield rate to produce chips using its own FoWLP technology.
Source: Lee Min-hyung, Koreatimes
www.koreatimes.co.kr/www/news/tech/2016/06/133_206979.html
Ultra-Dense 3-D Packaging for IoT
Smoltek AB is dedicated to superseding Moore’s Law by branching out alternative methods to solve the major bottleneck facing further miniaturization with its 3-D carbon-based nanostructure interconnects. According to Smoltek, the resulting more efficient 3-D electronics will be ideal to advance the IoT market Smoltek claims that the packaging combines ultra-thin CMOS layers into nearly monolithic high-density structures and enables ultra-dense packaging beyond Moore’s Law.
Source: Smoltek http://www.eetimes.com/document.asp?doc_id=1329757&print=yes
MEMS broadens its horizon by integrating sensor functions
According to Yole MEMS market will grow 9% to $20 billion in 2021. While consumer inertial sensors business slows, RF filters, MEMS microphones and emerging MEMS gas and optical sensors will increase strongly. Furthermore, the demand for multifunctional data processing will increase the MEMS integration level. “There will be a big change as MEMS companies move out of the business of supplying MEMS, and into the business of integrating sensor functions,” suggests Jean-Christophe Eloy.
Source: EEtimes http://www.eetimes.com/author.asp?section_id=36&doc_id=1329686&page_number=1
Worldwide Smartphone Sales to Grow 7 Percent in 2016
According to Gartner, Inc. global smartphone sales will slow down and will no longer grow in double digits. In 2016 smartphone units will grow 7% and reach 1.5 billion units. The growth is mainly driven by demand for low-cost smartphones in emerging markets, such as China and India and for affordable 4G smartphones. Furthermore there is also a market dynamics towards emerging Chinese brands:
“In a slowing smartphone market where large vendors are experiencing growth saturation, emerging brands are disrupting existing brands’ long-standing business models to increase their share,” said Anshul Gupta, research director at Gartner.
Source: Garnter, Inc. http://www.gartner.com/newsroom/id/3339019
Globalfoundries expands into Chinese 300mm wafer fab
Globalfoundries Inc. plans to upgrade an existing semiconductor facility in Chongqing, China for their 300mm technology in 2017. The fab will operate as joint venture with the process technology coming from Globalfoundries Singapore. The new manufacturing capacity will be used for CMOS and SOI processes from 130nm down to 40nm.
Source: Peter Clark, EEtimes, http://www.eetimes.com/document.asp?doc_id=1329797
STATS ChipPAC’s Fan-Out Wafer Level Packaging Shipments Exceed 1 Billion Units
STATS ChipPAC Pte. Ltd. announced today that it has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package.
Source: http://www.marketwatch.com/story/stats-chippacs-fan-out-wafer-level-packaging-shipments-exceed-1-billion-units-2016-05-10-161604036
Panel demand picking up, say IC firms
Short lead-time orders for small-size panels are flowing in while orders for large-size panels have been picking up. Taiwan-based analog IC and LCD driver IC firms are expected to post revenue growth in the second quarter of 2016, according to industry sources.
Source: http://www.digitimes.com/news/a20160512PD208.html
What’s Next For NAND?
NAND flash memory is a key enabler in today’s systems, but it’s a difficult business. NAND suppliers require deep pockets and strong technology to survive in the competitive landscape. And going forward, vendors face new challenges on several fronts.On one front, for example, the overall NAND market is currently in the doldrums, amid soft product prices and a mild capacity glut. Demand is expected to rebound in the second half of 2016, although there is still uncertainty in the market.
Source: http://semiengineering.com/whats-next-for-nand/
First Quarter 2016 Silicon wafer shipments increase quarter-over-quarter
Global silicon wafer area shipments increased during Q1/2016
Worldwide silicon wafer area shipments increased during the first quarter 2016 when compared to fourth quarter 2015 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. Total silicon wafer area shipments were 2,538 million square inches during the most recent quarter, a 1.3 percent increase from the 2,504 million square inches shipped during the previous quarter. However, new quarterly total area shipments are 3.8 percent lower than first quarter 2015 shipments.
Source: http://www.semi.org/en/first-quarter-2016-silicon-wafer-shipments-increase-quarter-over-quarter
Moore’s Law Is Dead. Now What?
Shrinking transistors have powered 50 years of advances in computing—but now other ways must be found to make computers more capable.
Source: http://www.technologyreview.com/s/601441/moores-law-is-dead-now-what/
Worldwide semiconductor manufacturing equipment billings increased 11% y/y to US$10.5 billion in 2Q16
Worldwide semiconductor manufacturing equipment billings reached US$10.5 billion in the second quarter of 2016. The billings figure is 26% higher than the first quarter of 2016 and 11% higher than the same quarter a year ago.
Worldwide semiconductor equipment bookings were $11.9 billion in the second quarter of 2016. The figure is 17% higher than the same quarter a year ago and 27 % higher than the bookings figure for the first quarter of 2016.
Source: Semi http://www.emsnow.com/npps/story.cfm?pg=story&id=59490
Updated Semiconductor Outlook for Internet of Things
Total IoT semiconductor sales are still expected to rise 19% in 2016 to $18.4 billion, but the updated forecast reduces the market’s compound annual growth rate between 2014 and 2019 to 19.9% compared to the original CAGR of 21.1%. Semiconductor sales for IoT system functions are now expected to reach $29.6 billion in 2019 versus the previous projection of $31.1 billion in the final year of the forecast. This is mostly due to lower sales projections for connected cities applications (such as smart electric meters and infrastructure).
Source: IC Insights; http://www.icinsights.com/news/bulletins/Updated-Semiconductor-Outlook-For-Internet-Of-Things/”
Renesas, TSMC put flash into 28nm MCUs
Renesas Electronics Corp. is working with foundry partner TSMC on a process module to enable the inclusion of embedded flash non-volatile memory in 28nm automotive microcontrollers.
The non-volatile memory will be Renesas Metal-Oxide-Nitride-Oxide-Silicon (MONOS) technology and automotive MCUs, scheduled to sample in 2017 and go into mass production in 2020.
Source: Peter Clarke, EE Times; http://www.electronics-eetimes.com/news/renesas-tsmc-put-flash-28nm-mcus”
ASE submits merger bid to Chinese, US watchdogs
Advanced Semiconductor Engineering Inc (ASE) has submitted a NT$128.7 billion (US$4.1 billion) bid to take over Siliconware Precision Industry Co (SPIL) to Chinese and US competition watchdogs to proceed with the planned merger. This brings the merger one step closer after the takeover bid was filed with the local competition agency about two months ago.
ASE has applied to the competition agencies in the US and China to form a holding company with SPIL.
Source: Lisa Wang, Taipei Times; http://www.taipeitimes.com/News/biz/archives/2016/09/07/2003654625
Actions Semiconductor Enters Into Definitive Merger Agreement for Going Private Transaction
Actions Semiconductor Co., Ltd., one of China’s leading fabless semiconductor companies that provide comprehensive portable multimedia and mobile internet system-on-a-chip (SoC) solutions for portable consumer electronics, has entered into a definitive merger agreement pursuant to which the Company will be acquired by a consortium of investors, including Supernova Investment Ltd. and other certain shareholders of the Company. The merger is currently expected to close during the last quarter of 2016. If completed, the merger will result in the Company becoming a privately-held company and its ADSs will no longer be listed on The NASDAQ Select Global Market.
Source: PR Newswire; http://www.prnewswire.com/news-releases/actions-semiconductor-enters-into-definitive-merger-agreement-for-going-private-transaction-300326325.html