Leading edge chemistry, equipment, and process solutions for the semiconductor industry
- Advanced semiconductor packaging solutions
- Chemicals for electroless and electrochemical deposition of Cu, Ni, Pd, Sn, and Au
- Cu Damascene process solutions
- MultiPlate: an innovative Electrochemical plating tool
- High tech clean room manufacturing
- Pad Metallization (ENEPIG, ENEP, ENIG)
- RDL and pillar plating
- Through via filling
- Double side plating
- Cu Damascene
Plating Tool - MultiPlate
- MultiPlate®: Atotech’s first semiconductor plating tool addresses future industry requirements such as cost effectivity and superior process performance for manufacturing of electrochemical packaging solutions. MultiPlate® is designed for single and double sided plating, through hole filling and high speed pillar plating. The tool is compatible with both wafer and panel size substrates (silicon, glass, etc.) and can be customized according to the individual production requirements.
RDL and pillar plating
- Spherolyte® Cu/Ni/Sn/Au: Our Spherolyte® portfolio fulfills latest semiconductor packaging demands for electrochemical deposition of copper, nickel, tin and gold at high speed and low costs. The products include various base electrolytes and additive systems and demonstrate exceptional results for plating of redistribubtion layers (RDL) and Pillar structures used in many consumer applications.
Pad metallization and RDL housing
- Xenolyte® ENEPIG/ENEP/ENIG: Pad/Under Bump Metallization is used to protect the underlaying interconnects and provide a robust and stable solder joint connection to the IC substrate. Our electroless Xenolyte® plating process is a cost effective alternative to traditional sputtering technology. The portfolio includes pretreatment and plating chemistry for deposition of nickel, palladium and immersion gold used for solder bumping, wire bonding and wedge bonding on different surfaces.
- Immersion tin: Within the packaging industry immersion tin is recognized as a reliable surface finish to protect untreated Cu from oxidation and deliver a perfect base for soldering of Cu surfaces to IC substrates. Our Stannolyte® Sn offers a perfect solution to plate on Cu pads, where Cu is displaced by Sn in a molecular exchange reaction.
- Everplate®: Everplate® chemistries and process solutions are developed with a target of providing a cost-effective solution for the Cu Damascene process for technology nodes down to 22 nm. The portfolio consists of medium and high purity base electrolytes and additive suites tailored to meet application specific demands.
- Atomplate®: As the state of the art interconnect technology continues decrease in size, requirements for Damascene process defect levels, film purity and integration capability are becoming more and more challenging to meet. The Atomplate® additive suite is the product of a joint collaboration with Lam Research and is designed to meet the most stringent copper interconnect process requirements for technology nodes to 7 nm and beyond.
- Atompure® electroless: The newly developed Atompure Electroless product line will bring the electroless deposition of pure Cobalt, Copper and Nickel into the scope for metallization of sub 10 nm node chip interconnects.
High purity chemistry production
Cleanroom manufacturing for the semiconductor industry
We produce high purity chemistry according to the latest and most stringent semiconductor industry requirements. Our 1,500m² cleanroom manufacturing facility located in Neuruppin, Germany is equipped with highly automated manufacturing equipment and enclosed production environments to ensure efficient, safe, environmental, and cost effective production.
Did you know?
With the addition of MultiPlate®, we have the unique position of offering a one-stop shop when it comes to electroplating, providing high purity chemistry, plating equipment, and process development for ECD packaging.
2016, PDF, 3.400 KB
This article was originally published in Silicon Semiconductor.
As device geometries continue to shrink, semiconductor packaging technologies face constant challenges to remain relevant and economically viable. Need of the hour is to develop innovative approaches that cost-effectively address the emerging requirements. This article will explore the current challenges for advanced packaging and how they may be overcame by rethinking traditional manufacturing approaches.
2017, PDF, 1.200 KB
This article was originally published in Chip Scale Review.
The emergence of FOWLP has been directly linked to satisfying the requirements for consumer electronics, and particularly those of mobile devices. This article will explore the drivers behind fan-out packaging, the key processing challenges, and the requirements at the application level. It will also discuss why fan-out is the ideal packaging technology for future generation mobile devices, and will present a turnkey solution for manufacture within both wafer and panel formats.
2016, PDF, 560 KB
This article was originally published in Chip Scale Review.
As the industry moves towards smaller, faster devices, there is mounting pressure on all members of the supply chain to enable higher performance at lower cost.
The limitations of Moore’s Law are evident and advanced technology nodes are no longer providing a significant cost benefit. As a result, the industry has shifted its focus to advanced packaging as a means for providing enhanced performance and lower costs, i.e. “More than Moore.”
The primary drivers for this shift are improved performance, more functionality, and cost reduction. This article will discuss how these three drivers have led to the emergence of flip-chip packaging using pillars and the current and future challenges for Cu pillar technology.
2015, PDF, 2.250 KB
Investigations of intermetallic reactions between the Sn3.5Ag0.5Cu solder and two different UBM structures, Ni(P)/Au and Ni(P)/Pd/Au.