Leading edge chemistry, equipment, and process solutions for the semiconductor industry
- Advance packaging solutions with electroless and electrochemical deposition of Cu, Ni, Pd, Sn, SnAg and Au
- Electrochemical solutions for latest interconnnect technology – Damascene Cu and Co
- MultiPlate: an innovative electrochemical plating tool
- High tech clean room manufacturing
- Pad metallization with ENEPIG for power chips and memory
- RDL, µ-Vias and pillar plating for FOWLP and FC-CSP
- µ-Via and through silicon via plating for sensors and 3D stacking
- Double sided metallization for power chips , e.g. IGBT, MOSFETS…
- Interconnect metallization for logic, memory and power ICs
RDL, µ-Vias and Pillar plating for FOWLP and FC-CSP
- Latest packaging technologies as FOWLP require a variety of plating solutions for different structures. Cu for fine line RDL with and without filled µ-Vias, Cu pillars with and without Ni barrier layers and last but not least SnAg for solder caps on pillars. Paramount is the purity of the Cu deposit to improve the overall reliability. The purity of the Cu deposit determines the reliability of the whole package avoiding RDL cracks in FOWLP or micro voiding at Cu/solder interfaces
- Atotech offers the full plating package for pillars, µ-Vias and fine line RDL Highest purity Cu deposits for the toughest reliability requirements, be it RDL , µ-Vias or Cu pillars. One for all Cu solution. Our Cu electrolyte plates every structure: µ-Vias, fine line RDL and pillars
- Spherolyte Cu UF3: Pure performance for all Cu structures: RDL, µ-Via s and pillars
- Spherolyte Ni: Effective barrier layer between solder and Cu to avoid a void
- Spherolyte SnAg: Our latest product for a reliable interconnect with 2 % Ag
Double sided metallization for power chips, e.g. IGBT, MOSFETS...
- Modern IGBTs and power MOSFETs require metallization on both sides of a wafer. The standard way of sequentially plating first front and then backside often struggles with stress and warpage issues during wafer processing. Thin wafers, needed to embed dies in power packages, are especially prone to this effect. What we need is an effective stress and warpage reduction during wafer processing
- We offer an alternative process – simultaneous double side Cu plating on front and backside for effective stress and warpage mitigation with:
- Individual front and backside control of Cu thickness
- Taiko wafer processing capability
- Reduced process flow
- Tool and chemistry out of one hand
- MultiPlate® and Spherolyte® MD2: Our dream team for power ICs
Pad metallization and RDL housing
- Wire bonding or soldering – which surface is most suitable for your packaging solution? And how do you get the desired metal stack on an alloyed Al Wafer or on a Cu Wafer? Can this be done in a high volume manufacturing process? Is it reliable, proven for automotive or even harsher environments? All these are the typical questions and challenges which define at the end which metals should be plated for first level interconnects.
- Universal pretreatment i.e. Zincation process for all Al alloys and universal activation for Cu Wafers
- Automotive proven Electroless Ni – Electroless Pd – Immersion Au stacks
- Extremely high productivity processes in wet benches, processing 25 or 50 wafers at once
- Cyanide free processes
- High temperature resistant ternary Ni deposits
- Pure Pd deposits for improved reliability
- Xenolyte Pd HS: Pure Pd for improved wire bonding performance
- Xenolyte Ni TR: Ternary Ni deposit or high temperature resistance
- Xenolyte Au CF2: Cyanide free immersion Gold process
Interconnect metallization solutions for logic, memory and power ICs
- Next generation interconnect technologies demand extreme performance of wet metallization processes
- Compatibility with extremely thin seed layers for copper damascene BEOL interconnects
- Able to fill pre-plate openings well under 10 nm for both copper and cobalt interconnects
- Void-free, high purity Cu and Co
- Of highest importance is void-free interconnect fill. Increasingly dense and complex interconnect levels require yield numbers to be higher than ever.
- Atotech offers state of the art wet metallization chemistries for both Cu and Co interconnects
- Extreme purity requirements are easily met by using Atotech in-house developed chemistries
- Solutions for each metallization step are available, and are compatible with all state of the art ECD platforms
- Everplate 2X Plus: High performance additive suite capable of filling advanced damascene Cu technology nodes
- Atomplate Co: Electrolytic pure Co for MEOL interconnect technologies, capable of providing a true bottom-up fill
High purity chemistry production
Cleanroom manufacturing for the semiconductor industry
We produce high purity chemistry according to the latest and most stringent semiconductor industry requirements. Our 1,500m² cleanroom manufacturing facility located in Neuruppin, Germany is equipped with highly automated manufacturing equipment and enclosed production environments to ensure efficient, safe, environmental, and cost effective production.
Did you know?
With the addition of MultiPlate®, we have the unique position of offering a one-stop shop when it comes to electroplating, providing high purity chemistry, plating equipment, and process development for ECD packaging.
2016, PDF, 3.400 KB
This article was originally published in Silicon Semiconductor.
As device geometries continue to shrink, semiconductor packaging technologies face constant challenges to remain relevant and economically viable. Need of the hour is to develop innovative approaches that cost-effectively address the emerging requirements. This article will explore the current challenges for advanced packaging and how they may be overcame by rethinking traditional manufacturing approaches.
2017, PDF, 1.200 KB
This article was originally published in Chip Scale Review.
The emergence of FOWLP has been directly linked to satisfying the requirements for consumer electronics, and particularly those of mobile devices. This article will explore the drivers behind fan-out packaging, the key processing challenges, and the requirements at the application level. It will also discuss why fan-out is the ideal packaging technology for future generation mobile devices, and will present a turnkey solution for manufacture within both wafer and panel formats.
2016, PDF, 560 KB
This article was originally published in Chip Scale Review.
As the industry moves towards smaller, faster devices, there is mounting pressure on all members of the supply chain to enable higher performance at lower cost.
The limitations of Moore’s Law are evident and advanced technology nodes are no longer providing a significant cost benefit. As a result, the industry has shifted its focus to advanced packaging as a means for providing enhanced performance and lower costs, i.e. “More than Moore.”
The primary drivers for this shift are improved performance, more functionality, and cost reduction. This article will discuss how these three drivers have led to the emergence of flip-chip packaging using pillars and the current and future challenges for Cu pillar technology.
2015, PDF, 2.250 KB
Investigations of intermetallic reactions between the Sn3.5Ag0.5Cu solder and two different UBM structures, Ni(P)/Au and Ni(P)/Pd/Au.